Block vs Distributed RAM

The "Distributed" Ram is a Xilinx terminology, The Altera terminology doesn't call it this, but it can do something similar, in that they can use the registers in the LE's as ram cells. But this eats (In both Xilinx and Altera fabrics)

One distinguisher between the families in the Altera world is the sizes of the block rams available:

Personally I liked the way the Stratix II family is structured best, small 512 bit blocks, (Great for fifos and small rams. M4K rams, Good size for larger delay rams, etc, and large M-Rams (512 K Bits) fast cpu storage and/or large tables..

Lately, the have gone to a single larger sized ram. And although the are flexible in how you use them, it doesn't fit my designs very well.

We have one design that fits in a 2S30 device, but we are forced to use a 3C55 device because of the ram structures of the Cyclone 3 family. And it's getting worse, In both Xilinx and Altera families.

Pete