Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Bidirectional Differential IO

Hi,

Is it possible to have bidirectional differential IO's in Altera FPGA. (Any series).

Plz reply.

Regards,

Jaseel

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    As far as I understand, only differential SSTL is supported for memory. Particularly no output enable is provided for any LVDS standard, so anything similar to M-LVDS isn't supported. For lower bit rates, a pseudo differential driver using two outputs and separate LVDS receiver could probably be used.