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Altera_Forum
Honored Contributor
Honored ContributorBi-direction signal issues
Hi Guys, I met an issue for Bi-direction signals. When the state is for output from FPGA, the data is not correct... Please help me. So I have a top module and connect the inouts to a subm...
Altera_ForumHonored Contributor
Honored ContributorOK the issue is solved. The problem is: the other side is also sending data to FPGA during the period, so both sides are sending data, there is conflict~~
