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Altera_Forum's avatar
Altera_Forum
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8 years ago

Bi-direction signal issues

Hi Guys, I met an issue for Bi-direction signals. When the state is for output from FPGA, the data is not correct... Please help me. So I have a top module and connect the inouts to a subm...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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You dont show what rd_period or emif_cs_n and emif_R_nW. If these are setting the bus to 'Z', then you will be reading the values coming from off chip.

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Hi, they were always in "emif_cs_n = '0' and emif_R_nW = '1'" contition... That's why I think it's weird..