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Altera_Forum
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16 years ago

Benchmark - how to raise clock frequency?

Hello, currently I'm doing some benchmark evaluation (dhrystone) on my Cyclone III Evalboard "BeMicro". I'm using the Nios II/e for the simplest option. The benchmark tells me 0,124 MIPS/MHz,...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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Sorry, i didn't get that... Which timing violations do you mean? I don't have errors when compiling, but when i try to run the benchmark with the NIOS II IDE (Eclipse), either the download verify fails or the processor does not respond, if the PLL frequency is configured too high.

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Towards the end of the compilation, Quartus runs a timing check using TimeQuest. It will check that the design you made can be run at the frequency that you selected. When there is a timing violation it won't report an error but just a critical warning. You should check for those.

Check also that the input clock is correctly defined, at the correct frequency (open Timequest, and select "report clocks"). This is mandatory, to ensure that Quartus will optimise the design to cope with the frequency that you want to achieve.