Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorBenchmark - how to raise clock frequency?
Hello, currently I'm doing some benchmark evaluation (dhrystone) on my Cyclone III Evalboard "BeMicro". I'm using the Nios II/e for the simplest option. The benchmark tells me 0,124 MIPS/MHz,...
Altera_ForumHonored Contributor
Honored ContributorThis 215MHz value looks quite optimistic. According to Altera's document it was measured on a EP3C40F324C6. I guess you have a C7 or C8 on your board, that will be a bit slower.
Do you have timing violations when you recompile your design with a higher frequency? You can try and add some pipelines, it will help increase the fmax. As an example a Avalon MM pipeline bridge between the CPU instruction and data masters and the JTAG debug module usually helps.
