Beginners Questions on Qsys Integration

Hi,

I have some beginners questions. On my Cyclone V board I try to bring 8 LEDs to blink, using a 50 MHz clock pin. I started first with a VHDL implementation. When this worked, I made a second setup with Qsys. Here I used the default clock and the HPS, since I'm using a SoC FPGA board with HPS. As third component, I created a new component, including my delay file which should (later) adjust the clock pulses for blinking by write/writeline input. I adjusted everything, generated the qsys component. I included the resulting .qip into the project. I made the pin setup and ran the pin assignment .tcl script. Everything works.

Now, when I try to make the blinking frequency faster by setting hardcoded the number for CNT_MAX or tmp_delay, respectively, to a lower value in the delay file - then update, regenerate in qsys, compile and flash it on the board - nothing is different. I did refresh in Qsys. I even edited the component and rebuilt the qsys setup... I realized that even if I comment out the whole "cnt <= cnt + 1;" or change of tmp_pos, it still blinks as before.

It seems as if my delay file does not have any impact as long as I'm using the HPS and a regular timer. I suspected the naming "clk" and renamed to "clk50", still nothing different. When I comment out or change the same values in my setup in my first plain VHDL setup with the same code, I can see the differences.

What might be my problem here in the Qsys setup?

How to update a Qsys setup correctly, if one .vhd file changed?

How may I debug such a situation? Are there any possibilities, in case using the test environment or simulation? I'm just running free version and so far have no experiences with further testings.. :(

Thx in advance!!!

Here is my Qsys screenshot, and the delay file. I have two more short files. One file for access one of the 8 LEDs, and another Top Level file.

https://www.alteraforum.com/forum/attachment.php?attachmentid=9009

-- delay file
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY delay_ctrl IS
PORT (
    clk : IN STD_LOGIC;
    reset : IN STD_LOGIC;
    -- signal pos, here as OUT, in blinker, as IN
    pos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
    -- avalon interface inputs
    write : IN STD_LOGIC := '0';
    
    -- avalon writedata must be a multiple of 8 (QSYS)
    writedata : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'));
END delay_ctrl;
ARCHITECTURE delay_ctrl_arch OF delay_ctrl IS
CONSTANT CNT_MAX : INTEGER :=     1000000;
SIGNAL cnt : UNSIGNED(24 DOWNTO 0);
SIGNAL tmp_pos: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
SIGNAL tmp_delay : INTEGER := CNT_MAX;
BEGIN
-- write, writedata comes later..
    clock_proc : PROCESS(clk, write, writedata) -- TEST
    BEGIN
        IF reset = '1' THEN
            cnt <= (OTHERS => '0');
            tmp_pos <= "0010";
            tmp_delay <= CNT_MAX;
        ELSE
            IF rising_edge(clk) THEN -- TODO undo
                -- check delay
-- I commented this partly out, no difference with Qsys
                IF (cnt = tmp_delay) THEN
                    cnt <= (others => '0'); -- init array to '000...'
                    CASE tmp_pos IS
                        WHEN "1111" => tmp_pos <= "1110";
                        WHEN "1110" => tmp_pos <= "1101";
                        WHEN "1101" => tmp_pos <= "1100";
                        WHEN "1100" => tmp_pos <= "1011";
                        WHEN "1011" => tmp_pos <= "1010";
                        WHEN "1010" => tmp_pos <= "1001";
                        WHEN "1001" => tmp_pos <= "1000";
                        WHEN "1000" => tmp_pos <= "0111";
                        WHEN "0111" => tmp_pos <= "0110";
                        WHEN "0110" => tmp_pos <= "0101";
                        WHEN "0101" => tmp_pos <= "0100";
                        WHEN "0100" => tmp_pos <= "0011";
                        WHEN "0011" => tmp_pos <= "0010";
                        -- 0001 is already done
                        WHEN "0010" => tmp_pos <= "1111";
                        WHEN others =>
                    END CASE;
                    -- write output
                    pos <= tmp_pos;
                ELSE
                    cnt <= cnt + 1;
                END IF;
-- /end of comment
            END IF; -- rising_edge
        
        END IF; -- reset
    END PROCESS clock_proc;    
END delay_ctrl_arch;