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Altera_Forum's avatar
Altera_Forum
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13 years ago

Beginner Q: How do I slow down my counter?

Hello, so I'm trying to implement a simple 4bit counter,

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity counter is

port (clk, reset : in std_logic;

Q : out std_logic_vector(3 downto 0));

end;

architecture behav of counter is

signal temp : std_logic_vector(3 downto 0) := "0000";

begin

process (clk, reset)

begin

if(reset = '1') then temp <= "0000";

elsif (rising_edge(clk)) then temp <= temp + "0001";

end if;

end process;

Q <= temp;

end;

I assign clk to 50MHz oscillator clock on my de2-115(pin_y2) and I get all 4 leds to light up and stay like that. I am guessing the clock period is so small that it seems like they are constantly up. I would like to slow it down so it takes say, 0.5 seconds between LEDs count.

I tried using after 500000000 ns line at the end of elsif statement but that didn't do anything.:confused:

Looking into altera ftp tutorials didn't turn up anything, and using search here turn up some crazy stuff that is way out of my league at the moment.

Any help would be appreciated.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Using clock enables, something like that:

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.numeric_std.all;

    entity counter is

    port (clk, reset : in std_logic;

    Q : out std_logic_vector(3 downto 0));

    end;

    architecture dest_cont of dest_led is

    signal cont_reg, cont_prox : unsigned(24 downto 0);

    signal temp_reg, temp_prox : unsigned(3 downto 0);

    signal tick : std_logic;

    begin

    process(n_clr, clk)

    begin

    if ( n_clr = '0' ) then

    cont_reg <= ( others => '0' );

    temp_reg <= ( others => '0' );

    elsif( clk'event and clk = '1' ) then

    cont_reg <= cont_prox;

    temp_reg <= temp_prox;

    end if;

    end process;

    cont_prox <= cont_reg + 1 when ( cont_reg < 25000000 ) else

    ( others => '0' );

    tick <= '1' when ( cont_reg = 25000000 ) else

    '0';

    temp_prox <= temp_reg + 1 when ( tick = '1' ) else

    temp_reg;

    q <= std_logic_vector(temp_reg);

    end architecture dest_cont;