Forum Discussion
Altera_Forum
Honored Contributor
13 years agoUsing clock enables, something like that:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity counter is port (clk, reset : in std_logic; Q : out std_logic_vector(3 downto 0)); end; architecture dest_cont of dest_led is signal cont_reg, cont_prox : unsigned(24 downto 0); signal temp_reg, temp_prox : unsigned(3 downto 0); signal tick : std_logic; begin process(n_clr, clk) begin if ( n_clr = '0' ) then cont_reg <= ( others => '0' ); temp_reg <= ( others => '0' ); elsif( clk'event and clk = '1' ) then cont_reg <= cont_prox; temp_reg <= temp_prox; end if; end process; cont_prox <= cont_reg + 1 when ( cont_reg < 25000000 ) else ( others => '0' ); tick <= '1' when ( cont_reg = 25000000 ) else '0'; temp_prox <= temp_reg + 1 when ( tick = '1' ) else temp_reg; q <= std_logic_vector(temp_reg); end architecture dest_cont;