Basic MAX V Quartus question

Using Max V and

Quartus II 64-Bit Versions 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition

First question, what is expected before the primitive?

The code below gives this errow message

Error (10500): VHDL syntax error at mux_4_13.v(3) near text "primitive";

expecting "entity", or "architecture", or "use", or "library",

or "package", or "configuration"

primitive mux (led0,pb0,pb1);

input pb0,pb1;

output led0;

table

1 , 1 : 0

1 , 0 : 1

0 , 1 : 1

endtable

endprimitive

Second question.

Using the Web Edition the options in setting are as follows,

VHDL Version 1987,1993,2008

Verilog Versions 1995, 2001, System Verilog.

Which do I use or does it make a difference?

Thanks

Martin