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Altera_Forum's avatar
Altera_Forum
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13 years ago

Basic MAX V Quartus question

Using Max V and Quartus II 64-Bit Versions 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition First question, what is expected before the primitive? The code below gives this errow messag...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Yes, it does.

You're writing Verilog, but Quartus thinks the file is VHDL.