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Altera_Forum
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11 years ago

AvalonMM plus UniPhy DDR3 Controller (without SOPC or Qsys)

Hello! I read all forum topics twice and didn't find any answer. It whould be great if someone can help me! Quartus 11.1; StratixIVGX dev.board; At first I created ALTMEMPHY IP DDR3...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Now, I try to use the avl_beginbursttransfer signal according to Avalon spec...

Results're more interested than before.

Read diagram:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8776

After two read requests wairequest goes high. After several tacts readdatavalid goes high forever.

Write diagram:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8777

You can see that burstbegin = avl_beginbursttransfer after several tacts goes high forever.

I couldn't find any mistakes in code...Could anybody help me?

Thank you!