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MichaelB's avatar
MichaelB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Avalon to AXI implementation

Hi, currently I'm thinking to implement an own Avalon <-> AXI4 (MM) adapter and not using the QSYS autogenerated adapter. Currently we are using an AXI4 DMA which will stream data into the DDR4...
Pramod_atintel's avatar
Pramod_atintel
Icon for New Contributor rankNew Contributor
4 years ago

Hi Michael,

I am building a system with PCIe endpoint <-> AXI <-> HBM2.

I had a query regarding whether AXI interface able to support larger burstcount ? I have enabled burstcount greater than 32 in HBM controller.

Still, when I increase the burstcount in software to greater than 2, the HBM controller doesnt respond with data.

Did you face such issues interfacing AXI with HBM

Best Regards,

Pramod

  • MichaelB's avatar
    MichaelB
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi Pramod,

    we did a similar architecture where we had multiple masters connected to a single HBM2 channel + PCIe DMA access, too.
    Here the HBM2 burst controller seems to have a bug in some specific Quartus versions (Q20.4 and lower).

    We succeeded with a solution provided by Intel to patch the IP files after IP generation (yes, you won't be able to use the common tool flow anymore sadly). With Quartus 21.1 you will have this fix provided in the IP again.


    https://www.intel.com/content/www/us/en/support/programmable/articles/000086781.html

    For us it was a long way to debug this. Hopefully this will help you.

    FYI:
    We currently didn't switch to 21.1 because with 20.4 we got no timing violations in our design and with 21.1 the retiming process is not working properly again. With this we got tremendous timing violations and there we did not get a clear information from Intel support team why this is happening with a version upgrade.
    Let's see if this is fixed in further versions...

    Kind regards,

    Michael

    • Pramod_atintel's avatar
      Pramod_atintel
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hi Michael,

      Thanks for the reply.

      I am using Quartus 21.3 version. That should have solved the burst count issue, but still I am seeing the same issue.

      I will try replacing the auto-generated file from the link you sent and check.

      In 21.3, I am getting some timing violations, but most of them are false paths (signaltap related).

      Did you use AVMM or AVST for PCIe interface ?

      Best Regards,

      Pramod

      • MichaelB's avatar
        MichaelB
        Icon for Occasional Contributor rankOccasional Contributor
        4 years ago

        Hi Pramod,

        ok I would assume that should be resolved already.
        Could you share the configuration of the HBM2 controller IP file? Then I could compare it with our IP file.

        Maybe there are some further settings necessary to enable the burst support.

        We are using the PCIe AVMM (DMA) connected to the HBM2 (Stratix 10 MX).
        Do you use any module in between PCIe <-> HBM2?

        We faced some issue with the AXI bridge in between and just connected the AVMM of the PCIe directly to the HBM2 AXI ports.

        Kind regards,

        Michael