Avalon to AXI implementation

Hi Richard,

yes, I won't use the outstanding transactions due it is not supported by EMIF core anyway.

Furthermore I think it is not very beneficial to edit a standard component with an own component due the outstanding is not supported anyway by the EMIF core itself.

Would you recommend to use a CCB or an autogenerated CCB between two Pipeline Bridges? (mm_interconnect)

Here I would then configure without any outstanding transactions and just defining the BURST size.

Would this be a valid design for high throughput from AXI master to DDR?

Again this is my main reason why I opened this thread.

With > 3 Gbps I would get overflows on the AXI master side - here I'm running with 160 MHz @ 256b and don't know why I have overflows.
DDR is working with 200 MHz @ 512b and it doesn't make sense for me why I get overflows then - We faced such issues previously and we checked in simulation that Avalon <-> AXI (mm_interconnect) does not response fast enough with a valid indication.

Furthermore we figured out to do protocol conversion and CDC (AXI 160 MHz @ 256b <-> Avalon 200 MHz @ 512b) is even worse in throughput than doing the protocol conversion first and then the CDC from Avalon <-> Avalon only.

Here I really want to be sure to support a data rate > 10 Gbps which should be possible with a BURST size of 32 in a 160 MHz @ 256b domain.

Would you recommend to just set max. read/write outstanding to 0 and just do the connection with Avalon <-> AXI BURST/bitwidth conversion?

Kind regards,

Michael