Avalon to AXI implementation

Hi Richard,

yes, I recognised this, too, that here are some signals missing (EMIF core & Avalon CCB).

• Is there an option in the Avalon CCB & EMIF core to enable those?
• How can I create a custom component for an standard IP? Would this be a custom component instantiating the EMIF core?

I tried to edit the interface of those IP cores in the component section in QSYS but I cannot add further signals.

I already read through the EMIF user guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-emi.pdf) but I could not found any setting to enable/disable pending write transactions.

Currently I am using the autogenerated interconnect from QSYS to resolve 256b AXI (BL = 16) to 512b Avalon (BL = 8).

Here I did not see any errors in the QSYS only the hint that an Avalon adapter will be inserted between AXI <-> Avalon.

Are there any special settings of the mm_interconnect I have to configure to do the bus conversion?

From the documentation of the Platform Designer I assumed this will be done by mm_interconnect automatically.

Do you have any reference design (QSYS) where a AXI <-> Avalon connection with bitwidth conversion + burst conversion is done?

That would be helpful to understand the settings on both sides to align them for the best throughput performance.

Kind regards,

Michael