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MichaelB's avatar
MichaelB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Avalon to AXI implementation

Hi, currently I'm thinking to implement an own Avalon <-> AXI4 (MM) adapter and not using the QSYS autogenerated adapter. Currently we are using an AXI4 DMA which will stream data into the DDR4...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi @MichaelB

Sorry for the delay in response.

You may checkout the User Guide below for more information on the adapter autogenerated by Platform Designer.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer.pdf

Could you share a screenshot of the DDR4 EMIF core & Avalon Clock Crossing Bridges that shown you can edit the maximum pending read transactions but not the maximum pending write transactions?

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

  • MichaelB's avatar
    MichaelB
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi Richard,

    thanks for your reply!

    In the EMIF DDR4 & Avalon CCB settings I'd like to increase pending writes (CCB Avalon_M will write data to Avalon_S of DDR4):

    AXI_M (write) -> Avalon CCB -> DDR4

    AXI Burst length = 16 (data width = 256) & Avalon Burst length = 8 (data width = 512) based on my calculation:

    16*256 = 8*512

    Will the interconnect resolve data width conversion and align the bursts?

    Screenshots of CCB & EMIF:

    EMIF DDR4 parametersEMIF DDR4 AVM settingsAvalon CCB AVM settingsAvalon CCB parameters

    Let me know if you need further information!

    Best regards,

    Michael