Avalon-ST spec contradiction.

My interpretation: pay particular attention to the word "and" within Table 5-1.

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The source may only (assert valid and transfer data) during ready cycles.

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i.e. asserting valid is part of the act of transferring data, and that transfer only happens during a ready cycle. If you assert valid, and change data bits, while ready is not asserted - then I believe this is a violation of the protocol specification, for example.

Anyway, the answer to your question is yes, you can assert valid while ready=0.