Forum Discussion
Altera_Forum
Honored Contributor
9 years agoMy interpretation: pay particular attention to the word "and" within Table 5-1.
--- Quote Start --- The source may only (assert valid and transfer data) during ready cycles. --- Quote End --- i.e. asserting valid is part of the act of transferring data, and that transfer only happens during a ready cycle. If you assert valid, and change data bits, while ready is not asserted - then I believe this is a violation of the protocol specification, for example. Anyway, the answer to your question is yes, you can assert valid while ready=0.