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Altera_Forum
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11 years ago

Avalon MM: writedata and write

Hi, a beginner's question, when passing data from HPS to the FPGA I use the AVALON MM interface. Now I'm a bit in doubt, if it is better to check "write" and then fetch "writedata" into a reg (verilo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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In a summary, why checking for "write" anyway if it works perfectly w/o it?

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Short of posting your module and testbench, post simulation or signaltap waveform showing your problem?

The general problem sounds like your _hw.tcl is not in agreement with your .v as far as timing of the signals goes.