Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAvalon MM: writedata and write
Hi, a beginner's question, when passing data from HPS to the FPGA I use the AVALON MM interface. Now I'm a bit in doubt, if it is better to check "write" and then fetch "writedata" into a reg (verilo...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- In a summary, why checking for "write" anyway if it works perfectly w/o it? --- Quote End --- Short of posting your module and testbench, post simulation or signaltap waveform showing your problem? The general problem sounds like your _hw.tcl is not in agreement with your .v as far as timing of the signals goes.
