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Honored Contributor
Honored ContributorAvalon MM: writedata and write
Hi, a beginner's question, when passing data from HPS to the FPGA I use the AVALON MM interface. Now I'm a bit in doubt, if it is better to check "write" and then fetch "writedata" into a reg (verilo...
Altera_ForumHonored Contributor
Honored ContributorInitially, I did check "write". I struggled for about 15 days with it not upcoming in my setup. I had everything connected in QSYS together with a toplevel file, but it never worked. Eventually I figured out, not checking for "write", and my setup works perfectly since I did receive the data, though. I call this data "writedata", also AVALON MM and slave. I think I understand your point about retaining data or just connecting the wires i.e. using "reg" or "wire", however I don't grok why I receive "writedata" and no "write"!? And what is the sense of checking for an additional "write"?
In a summary, why checking for "write" anyway if it works perfectly w/o it?
