New Contributor
Frequent ContributorHi ,
I was doing my research and found out that the behavior is expected.
May I know why you are asserting the being burst transfer for a periodically.
If you are asserting the above signal, slave will make sure the burstcout, write and byteenable signals are stable in the bus.
So that is why slave is asserting the signal. Once wait request is de-asserted data will start to transfer. But if you see your waveform you are asserting the being burst transfer, periodically.
New ContributorSee the attached image for the setup. We wrote an Avalon MM master using VHDL. It is connected to an Arria V Avalon MM PCIe IP though an AVMM interconnect that is automatically generated by QSYS. The befinbursttransfer signal you mentioned above is a signal between the automatically generated interconnect and the instantiated PCIe IP. We do not have any control over that signal.
The AVMM master asserts the write signal in every clock cycle because we want to write in every clock cycle. This is however not possible because the AVMM slave (PCIe IP) asserts waitrequest whenever we start a new burst. What is the reason for this poor performance?
