Honored ContributorI understand that in Qsys, components are connected through the use of Avalon interface. What I am confused about is, where does NoC come on stage and what is the relationship between NoC and Avalon?
Honored ContributorThe Avalon interfaces are used by the components themselves and as interfaces between them and the fabric generated by QSys. The commands sent on the Avalon buses by the components are translated to NoC transactions by the QSys fabric, and those transactions are translated back to Avalon commands at the other end.
Honored Contributor???
Hmm, where would be a good resource to read about it than? I need more elaboration.Honored Contributorhttp://www.altera.com/literature/hb/qts/qsys_interconnect.pdf
Why are you interested in this information? If you just want to use QSys or make a custom component, you don't really have to know how the interconnection itself is done, you just need to provide standard Avalon interfaces.Honored Contributor... ... ... ...
Honored ContributorYou can't know everything about the insides of an FPGA anyway, so the question is rather to decide what information you need to know to do your job. In my opinion there should be very few cases where knowing how the NoC architecture actually works will be really helpful to an applications engineer. It is more useful to learn about the Avalon interfaces, how to create custom components and how to optimize a QSys design (http://www.altera.com/literature/hb/qts/qsys_optimize.pdf).
Honored ContributorThis goes into a little bit of the details of the NoC: http://www.altera.com/literature/wp/wp-01149-noc-qsys.pdf
Network-on-a-chip (NoC) is not an Altera invention so there should be plenty of material out there on the web that you can read up on. Like Daixiwen said it would be more useful coming up to speed on the Avalon-MM or AXI interface specifications than knowing how the NoC works.Honored ContributorHello Matrixofdynamism,
As the other posters have mentioned, NoC can be complex to describe in intricate detail. The bottom line is that it allows the system to make different design choices between the bus standard that is being used, and the interconnect between them. NoC will translate an Avalon or AXI transaction into a wide packet-based stream and route this through the interconnect to the targeted slave. With the different burst sizes and clock domains that may be used in a custom design, a NoC is not static, and will be created on-the-fly to match the required interconnect topology. Great to hear that you are joining the Altera team soon. Please direct message me your contact details, and I'll arrange to add this to your training. Regards Kris
