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Altera_Forum's avatar
Altera_Forum
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18 years ago

Avalon communication

Hey guys!

I've a design base on an NIOS, an IP i've developed and the ddr ip.

Here is the connection with a screenshot of my sopc builder project. http://mitch.53.free.fr/bordel/sopc.jpg (http://mitch.53.free.fr/bordel/sopc.jpg)

NIOS MA -- SA MY_IP MA -- SA DDR

As you can see When NIOS wants to reach some data of the memory its needs to make a request to my IP which will answer it.

I join a screenshot of the signal when my problem occurs. http://mitch.53.free.fr/bordel/wave.jpg (http://mitch.53.free.fr/bordel/wave.jpg)

If NIOS makes a read request, then my IP called "security_core_module" makes the same read request to the DDR module.

As you can see the signal for the request to the DDR are good and the DDR module answers my IP with the good values.

The problem appears when my IP asserts the readdatavalid signal and the data on the bus for the master avalon of NIOS. As you can see on the top of the picture it seems that the signal are not forwarded to the master. Then the system spend all its time to wait for an answer from my ip which have already provided it....

Do you have any idea why the master don't take in account the answer of my IP?

Is there anything wrong the way that I assert the signal?

Of course I've check in SPOC that I don't make any mistake in the configuration of the signal of my IP...

Thank you for support!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hi Romain

    The problemin the waveform you've sent it with the waitrequest signal. Nios asks to read, but is only told to wait a few clock cycles later. The waitrequest is, contrary to other Avalon signals, an asynchronous signal, meaning that your slave should assert it as soon as it gets a read/write request. It should release it only when the data has been read/written.

    Nir
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    The signal are all good!

    I solve my problem since my post. It was juste because I forgot to put "8" has a value for the max pending read request
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Great

    I didn't realize your module was accumulating accesses from the Nios and then executing them only after 8 have arrived. In this case it makes everything clear.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    FYI, if you are using the Altera DDR SDRAM controller it uses a max pending reads of 16. Typically up to 12-13 reads will be pending when a DMA reads from it, so overestimating this value is usually a good thing (and doesn't cost much in terms of extra hardware)