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Honored Contributor
Honored ContributorAsynchronous v. Synchronous Logic
Am (still) relatively new to FPGA development. Please bear with me. Am using an FPGA to monitor address/data lines on an old (very old) MPU. I need to capture when an address is asserted on t...
Altera_ForumHonored Contributor
Honored ContributorHi John,
Thanks for the thoughts. Am using an old 80196. Address is always valid on falling edge of ALE. Reads and writes are valid on rising edges of RDn and WRn. For each signal, the data remains valid for approximately 30ns AFTER the corresponding edge. While a rising edge ALE would work, the address remains valid (and subsequently the data remains valid) for the 30ns after the RDn or WRn transitions high. ME
