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Altera_Forum
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13 years ago

Asynchronous v. Synchronous Logic

Am (still) relatively new to FPGA development. Please bear with me. Am using an FPGA to monitor address/data lines on an old (very old) MPU. I need to capture when an address is asserted on t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Tricky,

Many thanks. There is very little that the always loop will interact with. So I can't forsee any race conditions. And the MPU is soooooo slow, a few ns here or there shouldn't be a problem. 8>)

Thanks again for the guidance....

ME