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Altera_Forum
Honored Contributor
Honored ContributorAsynchronous v. Synchronous Logic
Am (still) relatively new to FPGA development. Please bear with me. Am using an FPGA to monitor address/data lines on an old (very old) MPU. I need to capture when an address is asserted on t...
Altera_ForumHonored Contributor
Honored ContributorIt is perfectly valid - just bear in mind that the async solution cannot have its timing analysed and you run the risk of race conditions. It is only bad because you cannot garantee the timing and the timing will vary with temperature, and cause glitches.
As long as you can cope with these (major - ie. it might work for a bit, then not) problems, then theres no problem.
