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Honored Contributor
8 years agoAsynchronous input strobe detection
Hello,
We are using Cyclone IV EP4CE40F23I7 and we have an implementation for an interface to a DSP (ADSP-21489, AMI Interface), which is causing us some problems with timing. The fact is that our implementation is using asynchronous edge detection through a latch, as show in picture 1. We are aware that this is probably not the best implementation but is the one that allows us to achieve the required access times and it is working stable so far. With this solution we need a lot of timing constraints to relate the signals in both domains and be sure that we have the correct timing in our signals. We have done this combining “set_net_delays” on our sdc and some “GetMaxTimingPath” checks on a Tcl that we run after timing analysis (although there are probably best techniques to constraint signals in different clock domains). We do not always get good results in these checks, as they are not affecting routing. We would like to simplify and improve this implementation but at the same time we are trying to keep the access times as low as they are now. So we are analyzing different possibilities:- Detecting input strobes with clk_sys, as shown in picture 2. To which extent is this implementation less stable or more problematic than the one shown in picture 1?
- Keeping the implementation as picture 1, but try to constraint all the signals on the sdc, relating the signals in both clock domains, to get rid of the Tcl checks. Should this be possible? Is implementation in picture 1 against good practice recommendations?
- Any other ideas? Thank you!