Honored Contributor
Honored ContributorThanks for the reply!
Yes, we know that to avoid metastability problems the best solution is not to use the signals before a 2 flip-flop stage. The question is more about the implementation in picture 1: is this stable enough, taking into account that one of the flip-flops in the chain is in rd_strobe domain and the second one in clk_sys domain? Wouldn't implementation 1 and 2 have the same response in terms of metastability? Adding a third flip-flop in implementation 2 would solve metastability issues but will delay the accesses in comparison to implementation 1, as they will be detected with clk_sys edge and not inmediately with the edge of rd_strobe. We are working at 10 ns in the FPGA and supposed to achieve 90 ns mean read accesses (of 32 bit data which means 2 consecutive DSP accesses).
