Forum Discussion

New Contributor

2 years ago

Assistance Needed: Trouble Running Bare-Metal Code on second core Cyclone 5 HPS

I am working on intel cyclone 5 hps I have two cores in a processor Core 0 core 1, I want two code to run on two different cores core 0 and core 1 in bare metal . When I run in jtag mode it work...

Regular Contributor

2 years ago

We do not have any example design for running application on separate core.

However we do got an example design which uses the Nios II processor as a separate core solution.

https://www.rocketboards.org/foswiki/Projects/DeviceWideAMP

Regards

Jingyang, Teh

Forum Discussion

Assistance Needed: Trouble Running Bare-Metal Code on second core Cyclone 5 HPS

Recent Discussions

Part Status request

Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy

Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0

Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger

IBIS models GTS banks agilex 5E