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Altera_Forum
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15 years ago

Ask question about Altera FPGA's PLL

What's the max fanouts of the PLL's output clock?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

If you refer to the internal clock distribution, read about global clock nets in the respective device handbook. General, it won't be a problem to supply it to all lgic cells in your FPGA. If you mean the external clock output, read about the specification for the I/O standard of your choice.