Asic Equivalent Logic of a Stratix 2 design

Ahh...

The age old question of "gate' to FPGA resources.

First he easy answer - No, it is not correct to say "1 ALUT equals 4 logic gates and 1 logic register = 2 logic gates".

(an ALUT is upto an 8 input Boolean function)

(A Register is made up of much more then 2 logic gate, maybe as many as 10 -12)

But the real answer is much more challenging then that .

And every one you talk to will most likely give a different answer as well.

One itimized list I have heard used is to multiply the FPGA stated resources by 9 to 12 to get to ASIC gates. On average this is not a bad in the ball park guess.

Other info I have read on the subject might also say;

4 transistors = 1 gate (2 input NAND)

A memory bit (SRAM) consumes 6 transistors.

(You may have heard of a 6-T memory cell)

IBM counts all of the transistors (logic and memory) and divides by 4.

So….A 2S180 would look like this.

Logic gates 180k *12 (gates we claim in a LUT) = 2.16M

DSP gates = ~ 1M

(8mb memory *6) /4 = 12M

Clocks, test, length base buffer insertion, slew rate fixing

= 10% overhead of logic = .216M

So a 2S180 = 2.16 + 1 + 12 + .216 = 15.376 million gates.

Of course, in an ASIC they are 100% utilized

and in an FPGA or Structured AASIC you only use what you use.

So, if someone uses an Altera memory to gate ratio, it looks like a big part.

If the design is logic intensive, it looks pretty small.

I hope this helps.