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Altera_Forum's avatar
Altera_Forum
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18 years ago

AS config problem

Hi,

When I used Byetblaster(I also tried to use Usb blaster) download the config file to the EPCS64,Quartus2 report that : Can't recognize silicon ID for device. Does anyone know what a EPCS identifier is ?And I checked the AS Interface found that: the DCLK pin has a 26MHz clock signal,and the nCSO pin is a low level,but the nCE pin is a low level while it should be high.

Can anyone help me with this problem ?

Thanks in advance.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    nCE connect 10K to ground,I checked.

    When I attempt to program EPCS64,I found nCONFIG changed from high to low,and then high,but nCSO always high and nCE always low.

    Quartus report : Can't recognize silicon ID for device.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Looking a schematic on my side that I know should work , nCE should have a 10k to ground, and be connected to pin 6 of the USB blaster header. If the 10k was stuffed with a zero ohm that would cause this problem.

    When monitoring the nCE pin, does the "Low" level move at all when you are attempting to program it?

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi,

    Thanks for your help.

    Iam sorry I had make a mistake.The nCSO pin is a high level and the the nCE is low.

    I checked the schematics,Iam sure the schmatic is the same as the Datasheet ,and I measured the voltage on the MSEL pins, they are set the right position.Is there any other point that I can't think?
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi,

    It sounds as though when you start programming the cable hasnt disabled the FPGA access to the EPCS device. this is why you still see nCE low, this should be high as you correctly stated.

    can you confirm that your schematics meet the following design requirements as stated in the Cyclone II handbook(assume you are using Cyclone II)

    http://www.altera.com/literature/hb/cyc2/cyc2_cii5v1_06.pdf

    Fig 13-7 pg 13-20