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14 years agoAS and JTAG access to cyclone II device
Hello, I did a design that has both JTAG access and AS access to a single cyclone II device, and am looking to see if I did it correctly.
For the AS circuit, I just used the suggested circuit shown in figure 13-7 in the altera document: http://www.altera.com/literature/hb/cyc2/cyc2_cii51013.pdf, except the msel pins are pulled low. For the JTAG circuit I used the figure 13-22 of the same document. Its just the same as the recommended circuitry, using 2 2x5 headers, except NCE is driven differently depending on which mode you are in. I used a SPDT switch to determine this mode. When in one position (RUN or JTAG), it feeds a 0 to the NCE pin of the FPGA. If in the other position (PROG) it feeds PIN 6 of the AS header, which is also pulled-down through a 10k resistor. Is this the correct way to have both JTAG and Active Serial access to the FPGA using a serial device? Also if I am using the byte blaster cable to do the AS programming, is it correct to use standard AS, or fast AS, as determined by the msel pins? Thank you, any insight is very much appreciated!