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Altera_Forum
Honored Contributor
Honored ContributorArrow SOCkit DDR3 SDRAM controller?
Has anyone written a DDR3 SDRAM controller for the FPGA side of the SOCkit that they are willing to share? Or has anyone build a 'facade' type hardware component for the uniphy to allow it to be acce...
Altera_ForumHonored Contributor
Honored ContributorThanks. Do you mean this guide or is there a simpler version? http://www.altera.com/literature/hb/external-memory/emi_tut_qdr.pdf. The one I found is bigger than the data sheets for the old DDR SDRAM, hopefully there is something more digestible.
The reference design for the video server looks useful. Thanks for the pointer. I'll download now and have a look through. I'd taken this working example and ripped out the DMA stuff, just connecting the HPS to the SDRAM. https://github.com/zhemao/ddr3_dma_demo. Great to hear I don't need to use AXI. If there is a simpler Avalon MM style master I can use then that will be much simpler. In terms of clocks can my avalon mm master have its own clock or does it need to use the Uniphy one?
