Arrow SOCkit DDR3 SDRAM controller?

Have you looked at this design yet? http://www.rocketboards.org/foswiki/projects/sockitvideoipvipreferencedesign I don't think you want to attempt to create a memory controller since that would be way more work than using what already exists. When adding the Uniphy IP to your design make sure you read the user guide info that discusses the steps. It's not difficult to use but if you don't use the provided steps then I guarantee the design won't compile or the interface won't work properly.

You don't need to use AXI for your own IP. If you connect a mix of Avalon and AXI components Qsys will adapt between them. The only thing it won't be able to adapt are features that are supported in AXI but are not available in Avalon. If you haven't created a memory master before I would look at some examples (or maybe just use them). The Qsys tutorial has some masters that you stream data in and out of them and they connect to memory. You could also look at the master blocks in this design which have more features than the Qsys tutorial but they have better documentation: http://www.alterawiki.com/wiki/modular_sgdma. There are probably quite a few other mastering IP that you can take a look at up on the Altera wiki to borrow/use as a template.