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Honored Contributor
Honored ContributorArriaV FPP implemention
hi all , i want to configure the fpga through external CPU & CPLD, all the FPGA configuration pins are connected to REGISTERS in the cpld. the cpu can asset -nCONFIG , read nSTATUS & CONV_...
Altera_ForumHonored Contributor
Honored ContributorYou're on the right track.
This document has details on how to write your own custom controller: http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf Altera also has the Parallel Flash Loader (PFL) megafunction http://www.altera.com/literature/ug/ug_pfl.pdf‎ You could read that document for more info. Cheers, Dave
