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AlehTS's avatar
AlehTS
Icon for New Contributor rankNew Contributor
5 years ago
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Arria10 transceivers and CSI

Hello. I have a task to receive data from CSI sensor. This sensor has CSI bus with 1 clock line and 4 data lines. Data are transferred on both edges of the clock. The clock rate is about 1.5GHz....
  • Deshi_Intel's avatar
    Deshi_Intel
    5 years ago

    HI,


    Pls see my reply below.


    1. Does this mean, that it is not possible to receive data without embedded clock ?
    • Correct. Transceiver architecture is meant to receive data transfer with embedded clock
    1. And generally, is it possible to receive data from CSI source using transceivers ?
    • From Intel FPGA perspective, we don't support MIPI IP solution
      • So, unfortunately this is something beyond Intel support plan and you will need to explore by yourself
      • One thing that raise my concern is you mentioned long continuous of 1 or 0 data pattern transfer. This is bad for transceiver receiver architecture and it will caused CDR to loose lock. For typical high speed protocol application, it will trigger to send "IDLE" data pattern to keep the CDR locked if there is no active data transfer on-going.


    Thanks.


    Regards,

    dlim


AlehTS's avatar
AlehTS
Icon for New Contributor rankNew Contributor
5 years ago

Thank you, dlim.

Please clarify one thing: in Arria10 the transceiver bank has 6 channels and 2 reference clocks inputs. If incoming data have embedded clock, what the reference clocks are for?

I can suggest, that they are used by transmitter to generate high speed clock and they are compared with recovered clock in RX mode to make sure that pll is locked correctly.

May be here are some other purposes of ref_clk?

Thank you.

Best regards,

Oleg.