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TSuzu6's avatar
TSuzu6
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6 years ago

Arria10 transceiver PHY rx_control[] issue

Hi!

In our Arria10 device, transceiver phy is configured as below,

-Transceiver Configuration rules:Basic(Enhanced PCS)

-PMA configuration rules:basic

-Number of data channels:6

-Data rate:6144Mbps

-TX channel bonding mode:PMA and PCS bonding

-"Enable tx_pma_div_clkout port" is checked, division factor=33

We checked "Enable rx_seraillpbken port" and set to 1'b1 for serial loop back mode.

[result]

6 channels tx_control[1:0] are set to 2'b01.

But rx_control[1:0] of some channels are sometime different from 2'b01.

We attached the signal tap capture "WS000028.JPG"

WS0000028.JPG:

tx_control and rx_control signals are captured.

signal name description

tx_control[11:10]: tx_control[1:0] for channel 5

tx_control[ 9: 8]: tx_control[1:0] for channel 4

tx_control[ 7: 6]: tx_control[1:0] for channel 3

tx_control[ 5: 4]: tx_control[1:0] for channel 2

tx_control[ 3: 2]: tx_control[1:0] for channel 1

tx_control[ 1: 0]: tx_control[1:0] for channel 0

rx_control[11:10]: rx_control[1:0] for channel 5

rx_control[ 9: 8]: rx_control[1:0] for channel 4

rx_control[ 7: 6]: rx_control[1:0] for channel 3

rx_control[ 5: 4]: rx_control[1:0] for channel 2

rx_control[ 3: 2]: rx_control[1:0] for channel 1

rx_control[ 1: 0]: rx_control[1:0] for channel 0

Why are tx_control and rx_control not same ?

We suspect transceiver PHY reference clock jitter.

Cloud you tell reconfirm point ?

BR,

taira

14 Replies

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  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi Taira,

    No problem. I will keep the case open and waiting for your update in May.

    FYI... Malaysia is impacted by COVID-19 as well. I have been working from home and fully understand your pain point from not able to work from office.

    Thanks.

    Regards,

    dlim

  • TSuzu6's avatar
    TSuzu6
    Icon for New Contributor rankNew Contributor
    6 years ago

    ​Hi, dlim

    Thank you for your Information.

    I want to confirm your check points, But My office is closed for COVID-19.

    Maybe, until 6-May-2020.

    So I will reply, when I can confirm .

    Thanks.

    BR,

    Taira

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi Taira,

    From your signal_tap result, rx_control [5:0] looks fine while rx_control[11:6] result looks bad.

    • Is this failure trend consistent meaning failure always occurs on rx_control[11:6] ?
    • I presume the mapping is transceiver channel [2:0] is good while transceiver channel [5:3] is bad ?

    Yes, transceiver clocking performance could be a concern here.

    • Does resetting NativePHY IP helps to resolve the issue ?
    • I presume you are using fPLL ? Is the fPLL sitted closer to channel [5:3] or [2:0] ? Does changing to other fPLL helps to resolve the issue here ?
    • Also are you using dedicated refclk pin to clock the fPLL ? Else pls take note of below KDB known issue
    • https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2017/fb470823.html
    • You can try reduce the data rate from 6G to lower data rate to see if it helps
    • You can also compared the CDR lock status signal (rx_is_lockedtodata) between good channel and bad channel to see id CDR loose lock is causing the issue here
    • Finally pls measure the on board transceiver PLL refclk pin and CDR refclk pin clocking signal to ensure the clock source is clean and stable

    Thanks.

    Regards,

    dlim