Hi Taira,
From your signal_tap result, rx_control [5:0] looks fine while rx_control[11:6] result looks bad.
- Is this failure trend consistent meaning failure always occurs on rx_control[11:6] ?
- I presume the mapping is transceiver channel [2:0] is good while transceiver channel [5:3] is bad ?
Yes, transceiver clocking performance could be a concern here.
- Does resetting NativePHY IP helps to resolve the issue ?
- I presume you are using fPLL ? Is the fPLL sitted closer to channel [5:3] or [2:0] ? Does changing to other fPLL helps to resolve the issue here ?
- Also are you using dedicated refclk pin to clock the fPLL ? Else pls take note of below KDB known issue
- https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2017/fb470823.html
- You can try reduce the data rate from 6G to lower data rate to see if it helps
- You can also compared the CDR lock status signal (rx_is_lockedtodata) between good channel and bad channel to see id CDR loose lock is causing the issue here
- Finally pls measure the on board transceiver PLL refclk pin and CDR refclk pin clocking signal to ensure the clock source is clean and stable
Thanks.
Regards,
dlim
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