Forum Discussion
CheepinC_altera
Regular Contributor
6 years agoHi,
Sorry for the inconvenience due to the wiki page. For your information, I have emailed you the design ZIP to your email. Please let me know if you are still not receiving it.
Thank you.
A_MISHRA
New Contributor
6 years agoHello @cheepinc_Intel sir, actually our hardware was having issue. We are using ARRIA 10 FPGA(10AS066K2F40E1HG), and CLKUSR pin should be given with 100-125 MHz clock for transceiver bank calibration. But we have not given this clock , after providing 100 MHz clock to this CLKUSR pin, our transceiver bank started working , so our Arria10 Transceiver PHY Design also worked and our SFP test using Transceiver toolkit was successful after this change.
Thanks and regards,
Ajay Mishra