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Itai_a's avatar
Itai_a
Icon for New Contributor rankNew Contributor
1 year ago

Arria10 to DDR4 layout guidelines

Hi, In Table 265. Layout Guidelines on page 253 at document " External Memory Interfaces Arria 10 FPGA IP User Guide" what does tCK stand for in Clock Routing? Regards
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi,


We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.


Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.


tCK stand for clock cycle.

Let say your DDR4 is running at 1200MHz, then one clock cycle is 0.8333ns. (1/1200MHz)

Therefore in this case, 1.5 clock cycle is 1.25ns.




Regards,

Adzim