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Altera_Forum's avatar
Altera_Forum
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8 years ago

Arria10 HPS SPI, chip select issue

Hi, I am interfacing a SPI slave, which requires chip select to be held low, for the entire duration of transfer. But, looks like chip select is toggled after every byte transfer. Tried workaro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Two observation to add to it,

1. Along with configuring CS as GPIO, even I had to enable the corresponding CS bit in the SPI HPS register.

2. With CS as GPIO, MOSI, CS and CLK lines are having voltage levels, 0v to 3.3v. But for some reason MISO is having a voltage range of 3.3v to 1.6v. MISO is clamped to 1.6v. So ARM HPS SPI reads back 0xffff

When tried with workaround suggestion of changing the Clock phase, MISO is toggling properly between 0v to 3.3v as expeccted. But as mentioned above, with clock phase change, I am having issue with bulk write and bulk read.

Anybody has observed similar issue ? Any suggestion ?