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TG_GER's avatar
TG_GER
Icon for New Contributor rankNew Contributor
2 years ago

Arria10 FPGA config directly from TFTP

I have an ARRIA10 SoC FPGA, and the memory card need to supposed to be hardware write-protected. At the end only u-boot is present on the SD card. It should retrieve the FPGA configuration, kernel,...
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aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi TG_GER,


If I understood correctly, I think the peripherals.rbf should consider the total size of the ram which can be used in your system and it should consider the 4gb external ram in your design as well. I think the HPS EMIF interface will need to consider the 4gb external ram as well. Below is the reference regarding the early IO release.

https://www.intel.com/content/www/us/en/docs/programmable/683437/current/introduction.html#:~:text=1.-,Introduction,Interface%20(EMIF)%20if%20present.

"

Early I/O Release Use Cases

There are a few different reasons why you might choose to enable the Early I/O

Release feature of the Intel Arria 10 SoC FPGA device. The typical reason is to speed

up system boot and configuration time. By gaining early access to a large pool of

system RAM connected the HPS EMIF interface, the boot software can more efficiently

load the bulk of the FPGA configuration image from mass storage. Restricting boot

code to on-chip RAM typically impedes bulk transfers because of the limited code and

buffer space.



Thanks.

Regards,

Aik Eu