Forum Discussion

Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Arria10 Embedded Memory

I have a question about Embedded Memory. I plan to use Arria10's M20K block RAM with 2-Port RAM.

In figures 1 and 4 of the user guide, the input signal to the RAM block transitions at the falling edge of the clock. I could not find a hold time specification for the input of the RAM block, so am I correct in understanding that the timing in the figure is recommended?

We are not familiar with English, so please forgive us for posting machine-translated sentences.

I'm sorry to bother you when you're busy, but it would be helpful if you could teach me.

4 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Generally, timing analysis will take care of sufficient hold time. You'll notice that maximal A10 block RAM clock frequency is rather high, e.g. > 500 MHz. Respectively you can expect a low hold time requirement, probably < 1 ns.

    • Yamada1's avatar
      Yamada1
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Mr. FvM

      Thank you for your answer.

      It was very helpful.

  • Yamada1's avatar
    Yamada1
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Thank you for your answer.

    I checked the documentation.

    Even in the simulation waveform, the input to the RAM block was transitioned at the falling edge of the clock, so I recognized this as a recommendation.