Arria10 , Error by use Generic Serial Flash controller

Hi,

The reason that you are observing the issue on compiling the design is due to your Quartus project is setting it as Passive Serial. In order to use the "Generic Serial Flash Interface Intel FPGA IP" you will need to change your configuration mode to Active Serial.

You can go to "Assignments --> Device --> Device and Pin Options... --> Configuration --> Configuration Scheme = Active Serial"

or add the below line to "generic_flash_access.qsf"

set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"

set_global_assignment -name USE_CONFIGURATION_DEVICE ON

set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ

Hi,

I have tried to compile your latest design but does not observed any error. Could you provide me the detail of the error that you observed?

I run the Quartus Prime Version 18.0.0.219 by Administrator mode.

Processing -> Start -> Start Analysis & Synthesis

Then there are many errors such as :

Error(13225): Can't open VHDL or Verilog HDL file "ip/generic_flash_access/generic_flash_access_intel_generic_serial_flash_interface_top_0/intel_generic_serial_flash_interface_xip_180/synth/generic_flash_access_intel_generic_serial_flash_interface_top_0_intel_generic_serial_flash_interface_xip_180_tsjvvby.sv"

Error(13223): Verilog HDL or VHDL error: cannot open verilog file 'ip/generic_flash_access/generic_flash_access_intel_generic_serial_flash_interface_top_0/intel_generic_serial_flash_interface_xip_180/synth/generic_flash_access_intel_generic_serial_flash_interface_top_0_intel_generic_serial_flash_interface_xip_180_tsjvvby.sv'

The files exist but the compiler can't find them .

Hi,

Could you extract the qar file that you provided to see if you are still seeing the issue?

OK, I still wait for your answer

Hi,

Could you try the attach QAR file?

Hi,

May I know what is your PWD directory? May I know if you are able to goto a shorter PWD location?

The license file is locate at C:\QuartusLicense .

Hi,

What I mean is the location of your project? The reason is that Windows is not able to handle long directory.

The project loation is C:\FPGA2 , please check the report file .