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Honored Contributor
Honored ContributorArria V tranceiver clocking
Hello! I need to use all the 24 tranceivers inside the 5AGXFA5H4F35I5 chip. I try to connect them as mentioned in AV53002 Figure 2-31: Six Bonded Receiver Channels with Rate Match FIFO Enabled U...
Altera_ForumHonored Contributor
Honored ContributorIt seems to be soved. Only Quartus ver. 13.1 points me to reset connection.
[tx_analogreset(0)] must be the same as [~pll_powerdown(0)]. In this case only the comiler merges additional TX clock divider (which is reseted by ~pll_powerdown(0)) with others (which are - tx_analogreset())
