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Altera_Forum's avatar
Altera_Forum
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13 years ago

Arria V performance Vs Arria II

Hi,Just wondering if any others out there had experienced poor timing performance from Arria V in comparison to Arria II ?We have a fairly standard but high speed RTL design which we used to run happily at speed on Arria II but in porting it to Arria V on an equivalent part there has been a significant drop in ability to meet timing, at least 20% off.I've simplified the design (ie its just rtl no dependencies on inputs or transceivers or other physically different architecture between the two families) and checked timing constraints etc but still the performance seems poor in comparison on standard register to register timing in the same clock domain ... Using Quartus 64 bit Linux 13.0 SP1Thanks in advance for any experiences you can share in relative performance between Arria II and V.

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  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The two parts are at speed grade 5 and 4 respectively - Drop in timing performance seems to be in general across many internal paths of the device (ie nothing to do with i/o's or anything like that) .... Just seems to be generally worse in standard RTL timing with a c4 Arria V compared to a c5 Arria II which I wasn't expecting ... One thing I've noticed when looking at the failing paths is there seems to be a lot of paths where clock skew is higher than I'd expect (sometimes up to 2 ns) which isn't helping with meeting timing. Clocks are properly set and constrained and on proper inputs and global routing paths, just seems like a bad job is being done on balancing the clock tree perhaps ? In general it just seems that on a fairly standard, if largish, RTL design I'm just not getting the sort of performance I'd expect and wondered if anyone else had similar experience or whether I'm just missing something

    EP2AGX125EF35C5 -> 5AGXFB3H4F35C4
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Yes there is. One thing in particular we have noticed is that insertion/exit time to global buffers is SLOW. If you have signals on global buffers - likely your resets will get promoted - you may have better results doing a manual assignment to a peripheral or regional buffer