Arria V performance Vs Arria II

The two parts are at speed grade 5 and 4 respectively - Drop in timing performance seems to be in general across many internal paths of the device (ie nothing to do with i/o's or anything like that) .... Just seems to be generally worse in standard RTL timing with a c4 Arria V compared to a c5 Arria II which I wasn't expecting ... One thing I've noticed when looking at the failing paths is there seems to be a lot of paths where clock skew is higher than I'd expect (sometimes up to 2 ns) which isn't helping with meeting timing. Clocks are properly set and constrained and on proper inputs and global routing paths, just seems like a bad job is being done on balancing the clock tree perhaps ? In general it just seems that on a fairly standard, if largish, RTL design I'm just not getting the sort of performance I'd expect and wondered if anyone else had similar experience or whether I'm just missing something