Arria V PCIE

Hello...

Wondering if anyone out there is using PCIe on the Arria V. I'm Currently using PCIe on both cyclone IV and arria V, and they are very different. It looks like Altera has changed their PCIe core with Arria V... The Megawizard even looks very different.

Anyways... On the Cyclone IV i was able to use a wrapper that the megawizard produces to shrink the large number of ports to clk, resets and transceiver input and outputs.

module top_example_chaining_top (

// inputs:

free_100MHz,

local_rstn_ext,

pcie_rstn,

refclk,

req_compliance_push_button_n,

rx_in0,

rx_in1,

rx_in2,

rx_in3,

usr_sw,

// outputs:

L0_led,

alive_led,

comp_led,

lane_active_led,

tx_out0,

tx_out1,

tx_out2,

tx_out3

)

;

I used this to instantiate the core in my RTL but for the ARRIA V there is no such file. I also noticed that the ipcore ports are slightly different. I do know that we are given a QSYS file, i've opened this but it doesn't seem like much help.

Basically I'm looking for a similar top_example_chaining_top.v file (core wrapper) for the ARRIA V... I've looked into recreating it but it calls a lot of modules that are device specific. I'm currently on the pinout stage and would like a quick way of confirming that the pin placement is correct.

Any input would be much appreciated...

Thanks.