Honored ContributorOn page 59 of the arria v gx, gt, sx, and st data sheet, in the i/o timing section is table 63 about programmable ioe delay. For device -C4, the D1_DELAY has available settings 0-31 with a value of 0.870ns. Is that per step (so 2 = 1.74ns) or is that for the whole 32 steps (so 1 ~ 27ps)?
Honored ContributorWhen I had similar questions to this I used the Quartus "Resource Property Editor" and just looked at the settings for the I/O delay elements. I'd recommend creating a simple design in Quartus, apply some timing constraints, and then look at those delay settings. You can adjust the TimeQuest delay constraints such that the delay element gets reprogrammed to a new value, so you can quickly confirm that your TimeQuest timing margins have changed by the appropriate delay change.
Cheers, DaveHonored ContributorThank you, I didn't know I could see it there. However, No matter what I change the D1 Delay value to in the Assignment Editor, the properties still show "D1 Delay Chain" "0:0 ps" (same for D3 Delay Chain 0,1). I recompiled, restarted Quartus and Chip Planner, but still no effect on the values. Is there another step I am missing?
Honored Contributor
