Arria JESD spanning 2 Transceiver Banks

I must connect a number of quad ADC devices with either 2, 3, or 4 JESD to the FPGA.

The number of lanes in the interface will affect the effective bits in the conversion (either 8 or 9) and of course the lane bit rate.

Since a bank in the FPGA consists of 6 transceiver channels, I would like to know what limitations exist such as:

1. Using 3 2-lane JESD interfaces in a single bank, is it possible?

2. Using JESD 4-lane interfaces, however, this would sometimes mean using 2 channels from one bank and 2 channels from the other (is it possible)?

Thanks